Syntax highlighting for VHDL, powered by WebAssembly

Tree-sitter parser and queries for vhdl, compiled to WASM for Lumis

A typescript based linter for vhdl

TypeScript-based VHDL Language Server (LSP) with optional GHDL integration

```sh git clone https://github.com/esdmr/vhdl-tb-gen.git node vhdl-tb-gen/index.js <input_file>.vhdl [<output_file>.vhdl] ```

Sigasi Magic HDL: analyze and verify Verilog, SystemVerilog, and VHDL projects from AI agents, over MCP.

Live Canon — read the AI-Writings canon as a navigable cell fabric, with 7 novel operations: NAVIGATE, CONFLUENCE, LINEAGE, GHOST, TICK, CLAIM, DRILL. 71 papers bundled (F98-F169). Polyformal: byte-exact with Python, C, Rust, Verilog, VHDL.

Vhdl language support for verdant-js

Adds support for the vhdl in Brackets text editor

The Quilt cell as a JavaScript library. 16-dial Q1.15 vectors, FNV-1a 64-bit state hash, byte-exact with the Python/C/Rust/Verilog/VHDL ports.

OpenClaw diffs viewer syntax highlighting language pack

Backend for terosHDL IDE

Xilinx Command Line ToolKit

Run Icarus Verilog compilation and VVP simulation from Node.js without installing native `iverilog` or `vvp` executables. Each request runs the `ivlpp`, `ivl`, and `vvp` WebAssembly stages in an isolated worker with an in-memory filesystem.

Hardware Description and Emulation Library

Library for simulating digital circuits and logic gates, providing a fluent interface for circuit design and analysis.

ACTAgent diffs viewer syntax highlighting language pack

Typescript example

TerosHDL backend

Rummy plugin for symbol extraction via antlrmap and ctags